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| SL23EP05 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock jitter: 20 ps-typ cycle-to-cycle jitter 15 ps-typ period jitter Low output-to-output skew: 30 ps-typ Low product-to-product skew: 60 ps-typ Wide 2.5 V to 3.3 V power supply range Low power dissipation: 16 mA-max at 66 MHz and VDD=3.3 V 14 mA-max at 66 MHz and VDD=2.5V One input drives 5 outputs organized as 4+1 SpreadThruTM PLL that allows use of SSCG Standard and High-Drive options Available in 150 mil 8-pin SOIC package Available in Commercial and Industrial grades Description The SL23EP05 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to five (5) clock outputs from one (1) reference input clock for high speed clock distribution applications. The product has an on-chip PLL which locks to the input clock at CLKIN and receives its feedback internally from the CLKOUT pin. The SL23EP05 is available with two (2) drive strength versions called -1 and -1H. The -1 is the standard-drive version and -1H is the high-drive version. The SL23EP05 high-drive version operates up to 220MHz and 200MHz at 3.3V and 2.5V power supplies respectively. The standard drive version -1 operates up to 167MHz and 133MHz at 3.3V and 2.5V respectively. The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is less then 2.0MHz or there is no rising edge. In this state all five (5) outputs are tri-stated and the PLL is turned off leading to less than 10 A of power supply current draw. Applications Printers and MFPs Digital Copiers PCs and Work Stations Routers, Switchers and Servers Digital Embeded Systems Benefits Up to five (5) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low power dissipation, jitter and skew Low cost Block Diagram Rev 1.0, May 21, 2007 Page 1 of 11 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP05 Pin Configuration 8-Pin (150 mil) SOIC Pin Description Pin Number 1 2 3 4 5 6 7 8 Pin Name CLKIN CLK2 CLK1 GND CLK3 VDD CLK4 CLKOUT Pin Type Input Output Output Power Output Power Output Output Pin Description Reference Frequency Clock Input. Weak pull-down (150k ). Buffered Clock Output Weak pull-down (150k ). Buffered Clock Output. Weak pull-down (150k ). Power Ground. Buffered Clock Output. Weak pull-down (150k ). 3.3V or 2.5V Power Supply. Buffered Clock Output. Weak pull-down (150k ). Buffered Clock Output, Used for Internal Feedback to PLL Input. Weak pull-down (150k ). Rev 1.0, May 21, 2007 Page 2 of 11 SL23EP05 General Description High and Low-Drive Product Options The SL23EP05 is a low skew, low jitter Zero Delay Buffer with The SL23EP05 is offered with High-Drive "-1H" and Standardvery low operating current. Drive "-1" options. These drive options enable the users to The product includes an on-chip high performance PLL that control load levels, frequency range and EMI control. Refer to locks into the input reference clock and produces five (5) the AC electrical tables for the details. output clock drivers tracking the input reference clock for systems requiring clock distribution. Skew and Zero Delay In addition to CLKOUT that is used for internal PLL feedback, All outputs should drive the similar load to achieve output-tothere is a single bank with four (4) outputs, bringing the output skew and input-to-output specifications given in the AC number of total available output clocks to five (5). electrical tables. However, Zero delay between input and Input and output Frequency Range outputs can be adjusted by changing the loading of CLKOUT relative to the banks A and B clocks since CLKOUT is the The input and output frequency range is the same. But, it feedback to the PLL. depends on VDD and drive levels as given in the below Table 1. VDD(V) 3.3 3.3 2.5 2.5 Drive HIGH STD HIGH STD Min(MHz) Max(MHz) 10 10 10 10 220 167 200 133 Power Supply Range (VDD) The SL23EP05 is designed to operate in a wide power supply range from 2.250V (Min) to 3.360V (Max). This power supply range complies with 3.3V+/-10% and 2.5V+/-10% standard power supply requirements used in most systems. An internal on-chip voltage regulator is used to supply PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. Contact SLI for 1.8V power supply version ZDB called SL23EPL05. Table 1. Input/Output Frequency Range If the input clock frequency is DC (0 to VDD), this is detected by an input frequency detection circuitry and all five (5) clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws less than 10 A supply current. SpreadThruTM Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP05 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. Rev 1.0, May 21, 2007 Page 3 of 11 SL23EP05 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min - 0.5 - 0.5 0 - 40 - 65 - - 2000 Max 4.6 VDD+0.5 85 85 150 125 260 - Unit V V C C C C C V Operating Conditions: Unless otherwise stated VDD=2.5V to 3.3V and for both C and I Grades Symbol Description VDD3.3 VDD2.5 TA 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature(Ambient) Commercial Industrial CLOAD Load Capacitance <100 MHz, 3.3V <100 MHz, 2.5V with High drive <133.3 MHz, 3.3V <133.3 MHz, 2.5V with High drive <133.3 MHz, 2.5V with Standard drive >133.3 MHz, 3.3V >133.3 MHz, 2.5V with High drive CIN CLBW Input Capacitance Closed-loop bandwidth CLKIN pin 3.3V, (typical) 2.5V, (typical) ZOUT Output Impedance 3.3V, (typical), High drive 3.3V, (typical), Standard drive 2.5V, (typical), High drive 2.5V, (typical), Standard drive Condition Min 3.0 2.3 0 -40 - - - - - - - - Max 3.6 2.7 85 85 30 30 22 22 15 15 15 5 1-1.5 0.8 29 41 37 41 Unit V V C C pF pF pF pF pF pF pF pF MHz MHz Rev 1.0, May 21, 2007 Page 4 of 11 SL23EP05 DC Electrical Specifications (VDD=3.3V): Unless otherwise stated for both C and I Grades Symbol Description VDD VIL VIH IIL IIH VOL Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage 0 < VIN < 0.8V VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (high drive) VOH Output HIGH Voltage IOH = -8 mA (standard drive) IOH = -12 mA (high drive) Power Down Supply Current IDDPD CLKIN = 0 MHz (Industrial) IDD Power Supply Current All Outputs CL=0, 66-MHz CLKIN - - 25 16 A mA CLKIN = 0 MHz (Commercial) Condition Min 3.0 - 2.0 - - - - 2.4 2.4 - Max 3.6 0.8 VDD+0.3 10 100 0.4 0.4 - - 10 Unit V V V A A V V V V A DC Electrical Specifications (VDD=2.5V): Unless otherwise stated for both C and I Grades Symbol Description VDD VIL VIH IIL IIH VOL Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage 0 Min 2.3 - 1.7 - - - - VDD - 0.6 VDD - 0.6 - - - Max 2.7 0.7 VDD+ 0.3 +/-10 100 0.5 0.5 - - 10 25 14 Unit V V V A A V V V V A A mA Rev 1.0, May 21, 2007 Page 5 of 11 SL23EP05 AC Electrical Specifications (VDD=3.3V and 2.5V) Symbol Description FMAX Maximum Frequency (Input=Output ) [1] Condition 3.3V High Drive 3.3V Standard Drive 2.5V High Drive 2.5V Standard Drive Min 10 10 10 10 25 40 47 45 - - - - - - - - - - - - 1.5 -100 -200 -150 -300 Typ - - - - - - - Max 220 167 200 133 75 60 53 55 Unit MHz MHz MHz MHz % % % % ns ns ns ns ns ns ns ns ns ns ps ps ns ps ps ps ps INDC Input Duty Cycle <135 MHz, VDD=3.3V <135 MHz, VDD=2.5V OUTDC Output Duty Cycle [2] <135 MHz, VDD=3.3V <135 MHz, VDD=2.5V tr/f3.3 Rise, Fall Time (3.3V) Measured at: 0.8 to 2.0V [2] Std drive, CL = 30 pF, <100 MHz Std drive, CL = 22 pF, <135 MHz Std drive, CL = 15 pF, <170 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <135 MHz High drive, CL = 15 pF, >135 MHz - - - - - - - - - - 30 40 - - - - - 1.6 1.6 0.6 1.2 1.2 0.5 1.5 2.1 1.3 1.2 90 100 4.4 100 200 150 300 tr/f2.5 Rise, Fall Time (2.5) Measured at: 0.6 to 1.8V [2] Std drive, CL = 15 pF, <135 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <135 MHz High drive, CL = 15 pF, >135 MHz t1 Output-to-Output Skew [9] All outputs CL=0, 3.3V supply, 2.5 power supply, standard drive All outputs CL=0, 2.5V power supply, high drive t2 Delay Time, CLKIN Rising Edge to CLKOUT Rising [2] Edge PLL Bypass mode PLL enabled @ 3.3V PLL enabled @2.5V t3 Part-to-Part Skew [2] Measured at VDD/2. Any output to any output, 3.3V supply Measured at VDD/2. Any output to any output, 2.5V supply Notes: 1. For the given maximum loading conditions. See CL in Operating Conditions Table. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Rev 1.0, May 21, 2007 Page 6 of 11 SL23EP05 AC Electrical Specifications (VDD=3.3V and 2.5V) (cont.) Symbol tPLLOCK CCJ [2,3] Description PLL Lock Time[9] Cycle-to-cycle Jitter Condition From 90% of VDD to valid clocks presented on all output clock pins 3.3V supply, >66 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, >66 MHz, <15 pF, high drive 2.5V supply, >66 MHz, <30 pF, high drive Min - - - - - - - - - - - - - - Typ - 20 40 40 35 30 50 18 15 30 25 25 20 20 Max 1.0 50 100 100 90 60 125 50 35 75 60 60 60 45 Unit ms ps ps ps ps ps ps ps ps ps ps ps ps ps PPJ [2,3] Peak Period Jitter 3.3V supply, 66-100 MHz, <15 pF 3.3V supply, >100 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, 66-100 MHz, <15 pF, high drive 2.5V supply, >100 MHz, <15 pF, high drive Notes: 3. Typical jitter is measured at 3.3V or 2.5V, 30 C with all outputs driven into the maximum specified load. Rev 1.0, May 21, 2007 Page 7 of 11 SL23EP05 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS on the pins 6 and 4. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output (SSCLK) and the load is over 1 1/2 inch. The nominal impedance of the SSCLK output is about 30 . Use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve "Zero Delay" between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal feedback to PLL, and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between clocks and CLKIN. For minimum pin-to-pin skew, the external load at the clocks must be the same. Rev 1.0, May 21, 2007 Page 8 of 11 SL23EP05 Switching Waveforms Figure 1. Output to Output Skew Figure 2. Input to Output Skew Figure 3. Part-to-Part Skew Rev 1.0, May 21, 2007 Page 9 of 11 SL23EP05 Package Drawing and Dimensions 8-Lead SOIC (150 Mil) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Still air 1m/s air flow 3m/s air flow Independent of air flow Condition Min Typ 150 140 120 40 Max Unit C/W C/W C/W C/W Rev 1.0, May 21, 2007 Page 10 of 11 SL23EP05 Ordering Information [4] Ordering Number SL23EP05SC-1 SL23EP05SC-1T SL23EP05SI-1 SL23EP05SI-1T SL23EP05SC-1H SL23EP05SC-1HT SL23EP05SI-1H SL23EP05SI-1HT Notes: 4. The SL23EP05 products are RoHS compliant. Marking SL23EP05SC-1 SL23EP05SC-1 SL23EP05SI-1 SL23EP05SI-1 SL23EP05SC-1H SL23EP05SC-1H SL23EP05SI-1H SL23EP05SI-1H Shipping Package Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Package 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC Temperature 0 to 70C 0 to 70C -40 to 85C -40 to 85C 0 to 70C 0 to 70C -40 to 85C -40 to 85C While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, May 21, 2007 Page 11 of 11 |
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